The present invention relates to a semiconductor integrated circuit device in which a logic circuit and a memory block accessed by the logic circuit are incorporated.
Conventionally, memories corresponding to individual logic circuit blocks have been embedded on a system LSI to achieve performance improvement and power consumption reduction. FIG. 7 is a block diagram illustrating an example of a conventional semiconductor integrated circuit device. As shown in FIG. 7, a static random access memory (which will be hereinafter referred to as an “SRAM”) 51 having a size ranging from about several kilobits to about several hundred kilobits is used as a storage section for data which is required to be processed at high speed. This is because an SRAM has high random access performance and efficient compilability as well, such that capacity and bit width necessary for data processing can be combined easily. On the other hand, as a storage section for large volume data which does not need high-speed processing and has certain limited patterns, a general dynamic random access memory (which will be hereinafter referred to as a “DRAM”) 52 having a size on the order of megabits or more is provided (see non-patent literature 1, for example.)
Meanwhile, DRAMs which are different from general DRAMs have been also embedded on an increasing number of system LSIs in order to achieve not only performance increase and power consumption reduction, but also total cost reduction or the like obtainable by optimizing necessary memory capacity to a certain degree (see non-patent literature 2, for example.)
(Non-patent literature 1) Hideo Ohwada and six other persons ‘A single-Chip Band-Segmented-Transmission OFDM Demodulator for Digital Terrestrial Television Broadcasting’ 2001 IEEE International Solid-State Circuits Conference
(Non-patent literature 2) Toshiba Semiconductor Company, ‘Embedded DRAM technology’ (the search of which was performed on Sep. 25, 2003) Internet <http://www.semicon.toshiba.co.jp/prd/asic/index.html>